1. Field of the Invention
The present invention relates to a parallel adder with a carry between adjacent adding stages, each of which has two data input terminals and a carry-generating circuit having a carry input terminal and a carry output terminal. The carry-generating circuit generates a carry output signal from carry input signals to be added by the adding stage and a carry input signal applied to it.
2. Description of the Related Art
In modern computer technology, fast signal processing necessitates arithmetic/logic units (ALUs) which contain adders that are able to perform additions which also form the basis of the remaining arithmetic operations.
The function of such adders is to add N-bit data words, with the carry from the respective preceding stage being taken into account in calculating the respective next higher-order bit.
Serial adders are slow adders which process only one bit of the N-bit data word per clock pulse taking into account the carry. Parallel adders are faster and are therefore used in the ALUs of processors.
A fast method of parallel addition is known which uses "carry look ahead". In this method, a complex logic first determines all carries, and only then are the sums formed. As the number of bits per data word increases, the logic required to determine the carries becomes so complex that the arrangement becomes uneconomical.
A parallel adder which requires no such complicated logic (i.e., no carry look ahead) uses a carry-handling method known as "ripple through". The present invention deals with such an adder, for which the basic structure is shown in FIG. 1. Such a parallel adder has a number of adding stages corresponding to the number of bits of the data words. Each of the adding stages is fed with two data input signals and a carry signal from which it forms a sum, and possibly generates a carry signal to be forwarded to the next adding stage. The two data input signals correspond to the binary state values having that significance within the data words to be added which is assigned to the respective adding stage. A given adding stage can perform its arithmetic operation only when it has received the carry signal from the preceding adding stage. Therefore, a corresponding time elapses until the final result of the computation performed by the parallel adder is available.